1. Field of the Invention
The present invention relates to semiconductor packaging technology, and more particularly to flip chip and related chip scale semiconductor packaging technology.
2. Description of the Related Art
As electronic devices become smaller and more dense, greater demands are placed on the ability to establish efficient, reliable interconnections from a semiconductor chip to a substrate. There are at least three known methods for interconnecting chips to substrates. Those three methods are face-up wire bonding, face-up tape-automated bonding, and the flip chip method. Of these three methods, the flip chip method has often been chosen as a preferred method for semiconductor packaging, for it allows for the interconnection of high-density devices having a large number of input and output paths. Specifically, the flip chip method is preferred because it provides short conductive leads from the chip to the substrate, a small device footprint, low inductance, high frequency capabilities, and good noise control.
A flip chip is a semiconductor chip that is mounted onto a substrate with the surface of the chip facing the substrate. Although several materials may be used to form an interconnection between the flip chip and the substrate, solder is one of the more commonly employed materials. In the solder interconnect process termed controlled-collapse chip connection (C4), a solder bump is deposited on a wettable conductive terminal on the semiconductor chip. The semiconductor chip is then aligned with the substrate so that the solder bumps is directly over a solder wettable terminal of the substrate. The solder bump is then tacked to the substrate and reflowed, creating an electrical and mechanical connection from the chip to the substrate as well as a path for heat dissipation.
The C4 process typically uses lead-based alloy as solder. For example, lead-tin alloys having a composition of three to five weight percent of tin have been commonly used. Although the use of such lead-based alloys allows for desirable processing conditions and reliable interconnect structures, the composition of the solder indirectly causes errors in devices on the semiconductor chip which are sensitive to radiation.
Most lead which is used to form C4 solder contains a Pb.sup.210 isotope which is a decay product of uranium. Pb.sup.210 is a radiogenic isotope which has a half-life of twenty-two years and which eventually emits alpha particles with an energy of approximately 5.5 million electron volts (5.5 MeV). The emission of such alpha particles from the lead solder bump leads to errors in radiation-sensitive devices present on a semiconductor chip bonded to the solder bump.
Incident ionizing radiation of an alpha particle that impinges upon a semiconductor chip produces a trajectory of electron-hole pairs within the semiconductor chip. The charge resulting from those electron-hole pairs, in turn, may collect in a potential well of a device on the semiconductor chip. For example, charge may collect in an empty storage capacitor of a memory device. If the amount of charge so collected exceeds a critical upset charge value, the storage device registers as being full rather than empty. Hence, an alpha particle may cause a single nonrecurring read error on a single bit of a memory array. In other words, an alpha particle emitted from a solder bump is a potential source of soft errors.
It is apparent from the preceding discussion that eliminating all alpha particle emitting isotopes in lead such as Pb.sup.210 would correspondingly lead to a reduction in radiation-induced soft errors in active devices. Although perhaps the most direct solution to the problem, completely eliminating radioactive isotopes in solder bumps has proven to be both difficult and very expensive. For instance, it is extremely difficult and costly to separate Pb.sup.210 from bulk lead. Lead isotope separation necessitates the use of large, expensive instrumentation such as an accelerator. Furthermore, because of its limited supply, it is very costly to use lead which naturally has a low abundance of the Pb.sup.210 isotope. In fact, such "low-alpha" lead typically costs between fifty and sixty times the cost of lead normally used to form solder bumps. Correspondingly, a need exists for a relatively inexpensive technique to reduce alpha particle emissions of lead-containing solder bumps.
Besides addressing the problem of soft errors by focusing on the solder composition itself, it is known that soft errors may be reduced by using error correction code. Error correction code reduces soft errors by providing a mechanism which both detects and corrects soft errors. Even if a storage capacitor is filled by charge resulting from an alpha particle, the error correction code will detect the error and return the device it to its original (and correct) empty state. Although error correction code has exhibited a degree of usefulness in reducing soft errors, room for improvement remains. In particular, error correction code is costly in that it creates memory redundancies and requires extra logic to implement. Correspondingly, a need exists for reducing soft errors without having to sacrifice memory or having to implement extra logic circuitry onto a semiconductor chip.
In view of at least the foregoing, it is apparent that an economical, improved solder bump which produces reliable, efficient interconnects while reducing or eliminating soft errors caused by alpha particle emissions is desired.